What You'll DoMain responsibilities include: * Physical Synthesis, * Place and Route, * Optimization, * Timing closure, * Verification of high speed chip blocks, * Design Floor Planning,Who You'll Work WithIn addition to working alongside talented colleagues, candidates will have many opportunities to learn through coaching and stretch assignment opportunities. They will be guided by feedback and support to accelerate the learning and maximize their knowledge.Who You AreEssential requirements: * BS/MS in Electrical Engineering or Computer Science * Understanding of ASIC design methodology and flow all the way from netlist to GDSII. * Understanding of Static Timing Analysis and timing closure * Knowledge in block level synthesis, place and route, timing closure. Knowledge of Cadence (RC, EDI, etc ) or Synopsys (DC, ICC, etc) design tools. * Understanding of design constraints and manipulation. Automation and programming-minded. Self-motivated, able to work independently or as a team player * Excellent English verbal and written communication skills. * Understands the big picture and detail oriented during execution.Why CiscoWe connect everything: people, processes, data, and things. We innovate everywhere, taking bold risks to shape the technologies that give us smart cities, connected cars, and handheld hospitals. And we do it in style with unique personalities who aren't afraid to change the way the world works, lives, plays and learns. We are thought leaders, tech geeks, pop culture aficionados, and we even have a few purple haired rock stars. We celebrate the creativity and diversity that fuels our innovation. We are dreamers and we are doers. We Are Cisco.