VTL Design and Verification Engineer

Individual will be responsible for developing transactor (xVIP) solutions for CXL/PCIe/Ethernet/5G based interconnect technology . Primary responsibilities include understanding standard specifications, develop architecture and micro-arch for the design and writing a synthesizable design using Verilog/System Verilog.

Individual must be able to create verification test plans and environments, testcase development, VIP usage, and the ability to debug of defects found through verification processes.

Individual would need to engage with customers for Deployment and R&D assistance.