Simulation tools are essential for the design and validation of digital circuits. They use different levels of abstraction to facilitate hardware/software co-design and co-validation. Architecture simulators, called Instruction Set Simulators (ISSs), provide high-level abstraction for fast functional verification and early design space exploration, while Register Transfer Level (RTL) simulators provide detailed circuit-level implementation for accurate analysis but with longer simulation times.

Faced with accelerated development schedules together with tool and resource constraints, hardware designers often start with RTL development and defer the construction of an ISS. However, as the design process progresses, the need to create ISSs becomes apparent, particularly for tasks such as software validation and design space exploration of next-generation hardware.

Creating ISSs manually presents significant challenges, as it is both time-consuming and error-prone. Further complexity is introduced by the need to ensure equivalence between ISS and RTL. There is therefore an urgent need for innovative methods to automate the generation of an ISS when the RTL is available.

The generation process of an ISS consists mainly of extracting architectural states and deriving instruction execution functions [1, 2]. An ISS is then constructed by seamlessly integrating the architectural states and the instruction execution functions, ensuring an accurate representation of the hardware's functional behaviour.

The goal of the thesis is to design a methodology implemented in a tool that takes low-level RTL models as input and automatically generates an ISS by exploiting recent advances in machine learning (ML) such as Graph Neural Networks [3], and compilation flows such as MLIR [4], in the field of electronic design automation (EDA). The expected result is a complete flow for the automatic generation of ISS from RTL, ensuring by construction the semantic consistency between the two levels.

The results of this thesis will be the subject of presentations at international conferences and in scientific journals.

References

[1] Zeng, Yu, Aarti Gupta, and Sharad Malik. "Generating architecture-level abstractions from RTL designs for processors and accelerators part I: Determining architectural state variables." ICCAD, 2021.

[2] Zeng, Yu, Aarti Gupta, and Sharad Malik. "Automatic generation of architecture-level models from RTL designs for processors and accelerators." DATE, 2022.

[3] Chowdhury, Subhajit Dutta, Kaixin Yang, and Pierluigi Nuzzo. "ReIGNN: State register identification using graph neural networks for circuit reverse engineering." ICCAD, 2021.

[4] Lattner, Chris, et al. "MLIR: Scaling compiler infrastructure for domain specific computation." CGO, 2021.

• Master's degree in Computer Science/Electronics.
• Good experience/knowledge in Machine Learning.
• Experience/knowledge in digital electronics design.
• Excellent programming skills in Python and C++. Proficiency in VHDL and/or Verilog programming will be a plus.
• Good analytical and experimental skills will be highly valued.

In accordance with the commitments made by the CEA in favor of the integration of people with disabilities, this job is open to everyone.