The Environmental Design and Architecture Laboratory (LECA), within the Digital Systems and Integrated Circuits Department (DSCIN), is a multidisciplinary technological research team comprising experts in hardware IP design and simulation tools. A key contribution of the Lab lies in its innovative methodologies and tools for automating model generation through machine learning techniques. In particular, the kMLeon tool facilitates the automatic generation of extra-functional models, such as performance and power ones.

The internship is associated with the TRISTAN European project [1], which aims to strengthen the European RISC-V ecosystem. It build upon ongoing work on automated performance model generation from RTL simulations using kMLeon, specifically for the CVA6 HW design of the OpenHWGroup [2]. The resulting models integrate with the QEMU emulator, enabling accurate performance estimations for various workloads while maintaining high simulation speed [3].

The intern will explore and extend the generalizability of this methodology along both SW and HW dimensions. On the SW side, RTL simulations are often compute-intensive due to large workloads, making data reduction essential to accelerate training data generation and model development. To address this, the intern will develop an innovative automated data reduction to optimize the process before RTL simulation. On the HW side, model generation has so far targeted single HW configurations. The intern will develop an innovative methodology to expand the model generation process to account for architectural variations, allowing for thorough design space exploration.

[1] https://tristan-project.eu

[2] https://github.com/openhwgroup/cva6

[3] https://riscv-europe.org/summit/2024/media/proceedings/posters/170_poster.pptx