Sr. Graphics Hardware Verification Engineer

Job description

Job Description

If you're interested in computer graphics and working with leading graphics hardware engineers on Intel's latest GPU/CPU architecture, then VTT has opportunities for you. VTT delivers Intel's 3D graphics, media, display, GPU, and Parallel Computing Technology.

This position is in 3D Graphics hardware front-end development where you will be working closely within a team of graphics hardware design/validation engineers, micro-architects, and architects on 3D Graphics blocks (subsystems) targeting a wide range of Intel's future generation processor products. The development environment is dynamic and fast-moving, focused on high-quality results, frequently entailing multiple projects under concurrent development. You will be encouraged to take informed risks, to continuously seek useful innovations and process improvements, and to have fun while doing so. This position is based in Folsom, CA, whence you will be collaborating with team members and other key partners located across multiple US and international sites.

Responsibilities include:

·  Analysis, interpretation, and assessment of hardware architectural specifications defining feature requirements for 3D Graphics blocks.
·  Definition and development of test plans, verification environments, validation components (bus functional models, trackers, checkers, scoreboards, test benches, etc.), functional coverage points, assertions, random and directed tests, random test constraints, etc. to validate 3D Graphics blocks (HDL code) at various levels of integration.
·  Integration and maintenance of HDL models and verification environments for simulation and ASIC logic synthesis.
·  Execution and debug of hardware simulations; achievement of functional test coverage objectives. Identification and closure of design and environment defects, including bug fixes.
·  Characterization and analysis of performance and power simulation results.
·  Debug of graphics hardware in emulation and/or silicon hardware environments; working with synthetic low-level tests as well as with stimulus from real-world applications and benchmarks and the graphics driver.

Inside this Business Group

The Platform Engineering Group (PEG) is responsible for the design, development, and production of system-on-a-chip (SoC) products that go into Intel's next generation client and mobile platforms. PEG strives to lead the industry moving forward through product innovation and world class engineering.

Posting Statement. Intel prohibits discrimination based on race, color, religion, gender, national origin, age, disability, veteran status, marital status, pregnancy, gender expression or identity, sexual orientation or any other legally protected status.

Desired profile

Qualifications

Requires Skills/Experience BS Degree in Electrical, Engineering Computer Engineering, or other related field 3+ years of relevant experience with a Bachelor's Degree, OR 2+ years with Masters Working Knowledge of computer architecture/organization fundamentals Working Knowledge of object-oriented programming in languages such as C/C++ or Python; Scripting in programming languages such as Perl Prior experience with logic design implementation and verification using (coding in) hardware description (HDL/RTL) and verification languages such as Verilog or System Verilog; applying good coding style Familiarity with definition and development/implementation of test plans, verification (simulation) environments, validation components, and tests Prior experience with usage/execution of logic simulation tools and environments; familiarity with broader ASIC development flows; hardware/hardware model debug Experience with Unix and/OR Windows OS usage Preferred Skills and Experience Familiarity with 3D Graphics architecture concepts, APIs, and standards - e.g., Direct3D, OpenGL; media/video codec standards; implementation of vector-based DSP/SIMD algorithms; Intel CPU architecture Knowledge of Coverage-based validation concepts and application - functional coverage points, assertions, random and directed tests, random test constraints, etc. using System Verilog or similar verification languages/tools; UVM/OVM verification methods Experience with Synopsys ASIC design tools - VCS simulator, Verdi, Design Compiler, IC Compiler Familiarity with formal verification methods - formal property verification (e.g., Jasper), high-level/algorithmic formal equivalence checking (e.g., HECTOR) Familiarity with digital hardware emulation and hardware debug tools - emulators, logic analyzers, etc.