SOC DFX Design Engineer

Job description

Job Description
General Job Scope- Utilizing industrial standard methodology such as Tessent MemoryBIST, IEEE 1687 IJTAG, SCAN and etc- Pick up fundamental concept in general DFx Design-for-Debug/Testability architecture, validation and integration knowledge. - Understand OVM and able use system Verilog for RTL design/validation task. Job Scope fall below 3 main areas. Actual assignment happen after joined: DFx micro-Architecture Engineer - Drive technical readiness TR, which mean understand customer requirement and further design relevant DFT/DFD/DFV features. DFT stand for Design for testability tester able access to PCH, DFD stand for Design for debug board able access the PCH and DFV stand for Design for validation Intel platform, customer board able to access to PCH- Require to understand all DFx sub IPs, knowledge require during research phase to implement in PCH DFx One stop DFx complete solution. - Besides DFx sub-IP, also require to familiarize other peripheral protocols such as I/O design protocols SATA, PCIe, USB & ETC, which also contain DFx features to be interact. - Enhancement on DFx features always as default expectation. This applied to all- Require to implement DFx design methodology into wide range of product streamline, such as client, Server, phone and high end laptop.- Good communication skill, a lot discussion happen across function group Tester group, platform team, customer team and etc before execution start. This is to ensure all the features requirement documented and implement in the chip. DFx RTL Design Engineer - Require RTL coding, pick up different RTL tool-based solution. Integrate all other DFx sub-IPs into one stop DFx complete RTL solution a.k.a DFx IP. Next insert this One Stop DFx complete logic a.k.a DFx IP into Main PCH chip. Along process will require signal/clock connection, timing convergence and etc. - Responsible to patch RTL logic for flawless area along execution phase. Ensure zero RTL design errors bug free as ultimate goal for DFx features. - Insert MemoryBIST logics to PCH, as part of the DFT features to enable High Volume Manufacturing HVM Memory screening through tests Post Silicon team. - Require good communication skill due to collaborate with geo-diverse teams full chip, structural design team, other IPs team in analyzing, debugging and identifying the root cause of issues that arise. - DFx Validation Test Engineer - Understand DFD, DFT or DFV features through spec reading, release test plan and develop relevant test script. Ensure all the RTL Design being validated well to eliminate design flawless to customer. - Execute Tests script DFx Tests with time guide, debug issues and implement fix. Report out test result timely and perform necessary test enhancement steps. - Drive test review with counterparts such as Pre-silicon full chip team, IP team, post silicon tester team, board team and etc. Thus require collaborate closely with other function group for test debug, analysis and root cause. - In additional, collaborate closely with Post silicon PDE team to enable HVM high volume manufacturing testing capability - Familiar DFx test Island Test environment for validation efficiency, enhancement purpose.

Inside this Business Group

Intel's Information Technology Group (IT) designs, deploys and supports the information technology architecture and hardware/software applications for Intel. This includes the LAN, WAN, telephony, data centers, client PCs, backup and restore, and enterprise applications. IT is also responsible for e-Commerce development, data hosting and delivery of Web content and services.

Desired profile

Qualifications

Qualify with Bachelor/Master degree in Electrical & Electronics or Computer System. Good knowledge in RTL integration and validation methodologies, preference given to those good in Verilog and C programming.Enjoy pick up protocol knowledge in I/O specifications such as USB2, USB3, SATA, PCIe. Best match if you do have knowledge in HVM, DFX, scan, JTAG and debug functionality. Genuine curiosity into microprocessors, computer system architecture and high speed design as well as producer consumer transactions. Also dedicated and proficient in digital state machine architecture and logic design.Working level mastery of Unix based design environment, industry standard digital design tools, scripting languages and ASIC flows If you obtain below personality.."Enjoys tinkering and teamwork to arrive at solutions to critical problems. Treat obstacles as opportunity and always stay positive. Great in communication and be able to work in different type of people"Please, apply the job, that's you!