RTL Design Methodology Engineer - Intel - Bangalore

Job description

Job Description

Develops and applies computer aided design CAD software engineering methods, theories and research techniques in the investigation and solution of technical problems. Assessing architecture and hardware limitations, plans technical projects in the design and development of CAD software. Defines and selects new approaches and implementation of CAD software engineering applications and design specifications and parameters. Develops routines and utility programs. Prepares design specifications, analysis and recommendations for presentation and approval. May specify materials, equipment and supplies required for completion of projects and may evaluate vendor capabilities to provide required products or services.

Inside this Business Group

The Platform Engineering Group (PEG) is responsible for the design, development, and production of system-on-a-chip (SoC) products that go into Intel's next generation client and mobile platforms. PEG strives to lead the industry moving forward through product innovation and world class engineering.

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Desired profile

Qualifications

The position is for a senior FE design automation and methodology expert in the area of RTL design and/or validation. You will be part of a FE design methodology team that is leading and driving industry leading design solutions and methodology for all designs at Intel. Your role will involve evolving design systems to improve reliability and velocity through methodology, automation, development, operation and refinement. Job qualification: In depth technical expertise and operational skills in RTL IP to SoC integration, IP hand-off, RTL quality sign-off lint, constraints etc., RTL hand-off to SD and/or pre-si validation. Proven track record of driving methodology/innovation in the above mentioned areas towards reduced cost, improved TTM and overall competitiveness of the designs. Must possess excellent stakeholder management & communication skills. Knowledge of languages like Perl, Python, shell and Verilog, System Verilog is a plus. Following skills are a must have depending on your area of expertise:RTL model build & releaseoSoftware build, release & deployment management, continuous integration tools and frameworks. oDeep understanding of SCM, build & release processes for agile and dynamic environment. IP hand-offoExpert understanding of design collateral and quality sign-off requirements for IP hand-offoThorough understanding of IP ecosystem from packaging & release on the IP to download and quality sign-off on SoC side.IP - SoC integrationoExpert understanding and knowledge in the SoC globals, fabrics and relevant architecture detailsoDeep technical knowledge in different needs and challenges of IP integration at SoC as well as exposure to different SoC integration methodologiesoExpertise in IC/SoC Design, integrating internal/3rd party IPs into SoC products.RTL quality and sign-offoLeadership experience in driving RTL quality closureoExpert understanding of methodology across CDC, RDC, low power, DFT and constraintsRTL hand-off to SDoExpertise in synthesis, timing analysis and timing optimized netlist generation. oMust have worked on latest UPF technologies and understand the various Power collaterals needed to synthesize design. oMust possess working knowledge of constraints and handling Power intent.Pre-Si validationoExpertise in testbench methodology and entire spectrum of verification management solutionsoExperience of working with industry leading RTL simulatorsoExperience of working with Pre-Si systems such as virtual platforms, emulation and/or FPGA-based prototyping solutions. We want to speak with you if: You architect, design, and deliver methodology solutions. You are responsible for rapid and accurate resolution of technical challenges, lead flawless implementations and integration of custom features. You excel at customer service, leadership and interface skills. You possess a can do attitude, are driven by research, problem solving, and thrive on challenges.