Pre Si Verification Engineer
Intermediate level job Santa Clara (Santa Clara County) Design / Civil engineering / Industrial engineering
Job description
Job Description
This opportunity is for a Pre-Si validation engineer with EIG in Santa Clara, CA.
You will develop pre-Silicon functional validation tests to verify system will meet design requirements. You will create test plans for RTL validation, defining and running system simulation models, and finding and implementing corrective measures for failing RTL tests. You will have an opportunity to analyzes and uses results to modify testing.
Minimum Qualifications:
Candidate must possess Bachelors or a Masters in Electrical Engineering with 3-5 years of experience in Pre-Si Verification.
· Sound understanding of functional verification fundamentals encompassing state machine verification, complex protocol verification, functional test strategies, directed and stress test generation, verification infrastructures and verification and/or debug flows
· Extensive knowledge of System Verilog and working knowledge of verification methodologies like OVM and UVM.
· Good knowledge on functional and code coverage
· Adept in programming and/or scripting (C++, Perl* and others) and be *conversant with flows and tools for VLSI logic design and/or functional verification
· Requires good communication skills as the role involves customer interaction.
Preferred Qualifications:
· Intel Chassis architecture, IOSF spec, UPF methodology, Intel tools and methodologies used for IP Verification
Inside this Business Group
The Platform Engineering Group (PEG) is responsible for the design, development, and production of system-on-a-chip (SoC) products that go into Intel's next generation client and mobile platforms. PEG strives to lead the industry moving forward through product innovation and world class engineering.
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