Packaging Engineer

Job description

Job Description

Microelectronic Packaging Engineers provide project management, package design/development and sustaining support for integrated circuit or semiconductor assemblies, various other electronic components and/or completed units. In this job, candidate will be responsible for the thermal/mechanical design, analysis, and development of electronic packages. Candidate will be solving packaging issues with RF components of varying technologies including WiFi, Bluetooth, GNSS, NFC. Defines overall package performance and specification to meet thermal, electrical, dimensional criteria for our products in both PC and mobile segments. Conducts tests and DOEs on basic materials and properties. Provides consultation concerning packaging problems and improvements in the packaging process. Develops and understands Packaging Manufacturing/Assembly processes so that designs are highly manufacturable in the outsourced Supply Chain Ecosystem. Knowledge of substrate technologies is critical. Responsibilities include package definition through HVM ramp and qualification.

Inside this Business Group

Intel is one of the largest suppliers of chips for the communications market. The Intel Communications group is focused on designing and building communications technologies such as Ethernet connectivity products, optical components, communications processing solutions and broadband products.

Other Locations

Oregon, Hillsboro; California, Santa Clara; California, Folsom;

Posting Statement. Intel prohibits discrimination based on race, color, religion, gender, national origin, age, disability, veteran status, marital status, pregnancy, gender expression or identity, sexual orientation or any other legally protected status.

Desired profile

Minimum Qualifications:
- BS or MS in Mechanical Engineering, Electrical Engineering, Physics, Optical Science, Materials Science/Engineering, or related technical field- 2+ years of experience with Package Assembly Technology: Components and Structure, Assembly Principles, Test Methods of Performance and Reliability, and Failure Analysis- 2+ years of experience with Packaging Physics, and in particular of Substrate Characteristics (Warpage), Bonding of Thin and Large Die and Properties of Under-Fill Materials- 2+ years of experience in Package Assembly Manufacturing Process and Practices and Ramp to High Volume Manufacturing- 1+ years of experience with Packaging Reliability Tests and Reliability Standards- 1+ years of experience with Probability and Statistics including Design of Experiments
Preferred Qualifications:
- 1+ years of experience in Semiconductor Device Physics and Process Engineering as related to Development of Package Assembly Technologies and Transfer to high volume Manufacturing- 1+ years of experience with Testing Systems, including Hardware and Software (Matlab, LabView)
- RF Component Packaging experience