IP System Validation Engineer (pre-silicon and post-silicon)

Job description

You will be a part of the USB IP SV COE team, and validate USB subsystem and use cases in an IP SV environment at both pre-silicon and post-silicon level. The position is a very open ended one, with scope from architecture POC (proof of concept) to RTL/silicon/board level validation and debug. In this position, you will review pertinent IP hardware and software specifications, create test plans, develop test content, execute the test content in FPGA/SLE(pre-si) and SoC/platform(post-si), and debug the failures by reviewing design, analyzing the debug signals/waveforms, and using variety of tools including, Logic Analyzers, LTB, ITP, protocol analyzers, and oscilloscopes. You also will be expected to leverage best known methods and content.

Desired profile

You must possess a Bachelor of Science degree in Electrical Engineering and/or Computer Engineering and/or Computer Science with 1 yr relevant experience, or a Master of Science degree in Electrical Engineering and/or Computer Engineering and/or Computer Science. Additional qualifications also include:

- Knowledge of Computer System Architecture
- Experience with C++ and/or C programming , Python
- Experience with logic design and/or understanding RTL.
- Understanding schematic and board layout, knowing how to trace the signals on board
- Experience with HW and SW debug, and debug tools such as logic analyzers, oscilloscopes, protocol analyzers, in-target probes(ITP) and Lauterbach (LTB)
- Excellent technical and problem solving skills
- A team player with good organizational and/or planning skills and solid verbal and/or written communication skills
- Highly motivated, curious, and have good lab skills (proper tool use, detailed note taking), and be keenly interested in finding and resolving silicon failures

Preferred skills:
- Familiarity with USB protocol or spec.
- Experience with high speed IO PHY design and debug.
- Experience with SVOS/Rocket/Maestro/Windows test environment will be a plus
- FPGA and/or SLE (emulation) usage for validation will be a plus