IP Structural Design Engineer

Job description

Job Description

Oversees definition, design, verification, and documentation for SoC System on a Chip development. Determines architecture design, logic design, and system simulation. Defines module interfaces/formats for simulation. Performs Logic design for integration of cell libraries, functional units and subsystems into SoC full chip designs, Register Transfer Level coding, and simulation for SoCs. Contributes to the development of multidimensional designs involving the layout of complex integrated circuits. Performs all aspects of the SoC design flow from highlevel design to synthesis, place and route, timing and power to create a design database that is ready for manufacturing. Analyzes equipment to establish operation infrastructure, conducts experimental tests, and evaluates results. May also review vendor capability to support development.

Inside this Business Group

The Platform Engineering Group (PEG) is responsible for the design, development, and production of system-on-a-chip (SoC) products that go into Intel's next generation client and mobile platforms. PEG strives to lead the industry moving forward through product innovation and world class engineering.

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Desired profile

Qualifications

Required Experience/Skills (Must Have)

·  M.S. in Computer Science, Computer Engineering or Electrical Engineering with 3+ years of experience with physical design, experience with block level synthesis/APR, timing closure, electrical rule checks, noise, power, formal equivalence, RV and layout DRC closure OR a BS with 4+ years of experience.
·  Strong skills on SNPS DC/ICC1/ICC2/Primetime tools

Preferred Qualifications

·  Experience with top level or sub full chip level design planning, pin assignment, block floorplanning, power grids, IO placement
·  Experience with timing model build, rollup flowsTop metal design and bumps, final design delivery, QA checksStrong automation skills with PERL, TCL or other programming languages
·  Exposure to Conformal LP FEV
·  Exposure to multi-voltage UPF based designs