IP Engineering Manager

Job description

Job Description

The IP Engineering Manager will lead a team of engineers to develop IP for Intel Programmable Solutions Group PSG FPGAs

Responsibilities:

·  Understand the Ethernet FPGA IP requirements from our end customers
·  Architect, develop, verify, and roll out IP products which implement/enable FPGA Ethernet functions
·  Plan group engineering work for product release cycles
·  Customize IP for specific customer design opportunities
·  Develop and mentor staff for technical and professional growth

Inside this Business Group

The Programmable Solutions Group (PSG) was formed from the acquisition of Altera. As part of Intel, PSG will create market-leading programmable logic devices that deliver a wider range of capabilities than customers experience today. Combining Altera's industry-leading FPGA technology and customer support with Intel's world-class semiconductor manufacturing capabilities will enable customers to create the next generation of electronic systems with unmatched performance and power efficiency. PSG takes pride in creating an energetic and dynamic work environment that is driven by ingenuity and innovation. We believe the growth and success of our group is directly linked to the growth and satisfaction of our employees. That is why PSG is committed to a work environment that is flexible and collaborative, and allows our employees to reach their full potential.

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Desired profile

Qualifications

Minimum Qualifications:

·  Bachelor's degree in Electrical Engineering or equivalent with at least 6 years of experience in Ethernet and FPGA development with 3 years of management experience.

Preferred Qualifications:

·  10 years of experience in Ethernet and FPGA development with 5 years management experience.
·  Proven track record in project management, team management, team development, and leadership
·  Experience with FPGA design tools such as Quartus Prime Experience with enabling FPGA transceivers/hardened blocks in design tools such as Quartus Prime
·  Experience with IP architecture, development, verification, and rollout
·  Experience with digital logic design with RTL Verilog or VHDL
·  Experience with parameterizable automation of logic generation and verification
·  Experience with implementing and verifying Ethernet IP functions
·  Experience with hardware debugging and validation using equipment such as Ethernet testers
·  Familiar with FPGA development and verification process, using Verilog or VHDL