HVM Testing Development Engineer Internship

Job description

The Digital Content Development Group is looking for motivated engineers to join the team to work in the highly challenging environment of product development across Intel's product families.
The product development engineers in this team work to support architectural definitions for testability features, verification and validation of reset and functional test capabilities.
MDO DCD HTD team is responsible to maintain Intel's design and manufacturing quality of baseline product to the external world by paving the way for test content development and product test enabling.

This engineering team is specifically responsible for paving the way for test content development and spearheading product test enabling for product engineers worldwide.

An intern with the team will be exposed and contribute to the work product of the team, through ownership of deliverable projects.

Responsibilities of the engineers may include:
- Support DFT Design and Architectural Validation teams
- Creating an infrastructure for test content development using advanced simulation and emulation tools
- Pre-Silicon development and validation of reset sequences and functional test capabilities and features
- Silicon debug to identify functional and DFT related bugs

The ideal candidate should exhibit the following behavioral traits:
- Strong spoken and written communication skills
- Strong problem solving and prioritization ability
- Independent and Inquisitive

Desired profile

Minimum Qualifications:
- Must be pursuing a BS in Electrical Engineering, Computer Engineering, Computer Science or other science/engineering related field.
- At the BS level only, must have the unrestricted right to work in the US without requiring sponsorship
- Minimum 3 months experience with Design for Test and Design for Debug usage experience (design/verification/validation experience preferred)
- Minimum 3 months experience with pre-silicon validation platforms is preferred: VCS & SVTB, EVE (ZeBu-Server) and Mentor (Veloce) FPGA H/W Emulators
- Minimum 3 months experience with Silicon debug and characterization of new products to identify and close silicon issues.
- Minimum 3 months experience with Tester Experience to support debug and characterization of silicon (ability to define and execute experiments is preferred)

Preferred Qualifications:
- IP based arch concepts are desirable