Similar Jobs Graduate Intern - FE IP Design

Job description

Job Description
Responsibilities may be quite diverse of an exempt technical nature. U.S. experience and education requirements will vary significantly depending on the unique needs of the job. Job assignments are usually for the summer or for short periods during breaks from school.Behavioral traits:Verbal and written communication skills.Team player and enthusiastic learner.As a digital design engineer in VLSI Frontend Design team he will be involved in large scale of system-on-chip SOC and digital intellectual propertyIP development, from the contribution at the early stage of design conceptual definition and hardware macro-architecture to digital logic design implementation, low-power friendly coding, functional verification, register transfer level RTL design quality check, RTL power analysis/optimization. The main areas of responsibility as Frontend Digital Design Engineer include:- IC design and EDA knowledge- Register-transfer level RTL design implementation- Functional simulation and debugging, code coverage analysis- Function block/module development for SOC and IP integration and release- RTL design quality and timing checking- RTL power analysis and optimization

Inside this Business Group

The Data Center Group (DCG) is at the heart of Intel's transformation from a PC company to a company that runs the cloud and billions of smart, connected computing devices. The data center is the underpinning for every data-driven service, from artificial intelligence to 5G to high-performance computing, and DCG delivers the products and technologies—spanning software, processors, storage, I/O, and networking solutions—that fuel cloud, communications, enterprise, and government data centers around the world.

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Desired profile

Qualifications

Candidates should have a BS or MS degree in Electrical Engineering, Computer Engineering or equivalent related field. - Experience, good knowledge in logic design and implementation, RTL simulation - Digital Signal Processing DSP wireless communication knowledge - RTL design and integration in Verilog/VHDL hardware description language - Experience with following EDA tools or similar: o Spyglass for linting, RDC/CDC o PowerArtist for RTL power analysis and optimization o Simulation tool: NCSIM or/and VCS Good communication skill and strong problem-solving skills