Electrical Validation Engineer
Internship Folsom (Sacramento County) Design / Civil engineering / Industrial engineering
Job description
Job Description
Develops and documents electrical validation requirements and tests for verification of Si designs. Investigates and resolves complex issues with hardware/BIOS/Firmware/Operating System implementations and recommends solutions. Uses analysis to resolve electronic issues.Completes compliance testing of DDR5 memory. Conducts DDR Post Silicon electrical validation for statistical based specs using lab bench test equipment. Collects platform level margin data and analyzes data eyes. Uses bench test equipment such as BERT, Oscilloscope, and logic analyzer to collect electrical validation data. Automates collection of characterization data where required. Correlates SIMBA pre-silicon simulation estimations to DDR platform margin results.Performs signaling simulations of DDR SI Tools and PCB designs
Inside this Business Group
The Data Center Group (DCG) is at the heart of Intel's transformation from a PC company to a company that runs the cloud and billions of smart, connected computing devices. The data center is the underpinning for every data-driven service, from artificial intelligence to 5G to high-performance computing, and DCG delivers the products and technologies—spanning software, processors, storage, I/O, and networking solutions—that fuel cloud, communications, enterprise, and government data centers around the world.
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Desired profile
You must possess the below minimum qualifications to be initially considered for this position. Experience listed below would be obtained through a combination of your school work/classes/research and/or relevant previous job and/or internship experiences
Minimum Requirements
- Candidates must have a Master's degree in Computer Science or Electrical Engineering + 2 years of experience in the following SIMBA or Sig Sim signaling simulation software Python scripting, SVOS, GPIB High speed signaling, signal integrity concepts, computer architecture