Design Rule- DFM Engineer

Job description

Job Description

NonVolatile Memory Device and Integration engineers are responsible for leading research and development in order to architect, develop and deliver leading edge nonvolatile memory technologies to high volume manufacturing. They contribute to defining process and device architectures, technology collaterals as well as develop scaling paths for leading edge memory technologies.

The scope includes development of new types of process and device architectures involving novel materials, structures and integration schemes to deliver industry leadership in density, performance, reliability and cost. They collaborate with technology development partners in defining goals, developing the vision, aligning strategy and driving fast paced silicon development to meet aggressive technology node cadences. In addition they work closely with the product and system teams to ensure seamless integration of the memory components into Intels system products as well as with the manufacturing Fabs to ensure a seamless technology transfer and ramp to support the full envelope of component and system products.

Intel NVM (Non Volatile Memory Process Technology Development Group) is responsible for developing state of the art NVM memory technologies like 3D-NAND & 3D-Xpoint. As a Design Rule/ DFM Integration Engineer, you will be responsible for initial tape-out of a new part type from start to finish including verification of design rules, and ensuring Design for Manufacturability guidelines are followed for die layouts and circuits. This job also involves assisting with layout check, Boolean operations, database issues, and being responsible for reticle/mask tape-out.

The responsibilities will include, but are not limited to the following:

·  Develop and maintain design rule document by having various interactions with key stakeholders such as process integration, design engineering, scribe design team, device, etc.
·  Use DF2, Cadence, K2View, Vcats, to develop and debug the rules.Interact with CAD to debug the rules and come up with methodologies and checks to understand the interaction with various mask and base layers.
·  Help in updating the Boolean logic/ generators by studying the sizing tables and Cailbre code.
·  Help in generating the Calibre code for the various sanity checks.
·  Perform DRC checks, layout vs. schematic and netlist extraction tools to ensure correctness in layout and also help in scribe test structures.
·  Drive diagnostic projects across multi-disciplinary teams to understand product and test structure failures and their interaction with layout and mask synthesized data.

Behavioral Requirements:

·  Good verbal & written communication skills with Excel, Visio & Power Point proficiency

This is an entry level position and will be compensated accordingly.

Inside this Business Group

Non-Volatile Solutions Memory Group: The Non-Volatile Memory Solutions Group is a worldwide organization that delivers NAND flash memory products for use in Solid State Drives (SSDs), portable memory storage devices, digital camera memory cards, and other devices. The group is responsible for NVM technology design and development, complete Solid State Drive (SSD) system hardware and firmware development, as well as wafer and SSD manufacturing.

Posting Statement. Intel prohibits discrimination based on race, color, religion, gender, national origin, age, disability, veteran status, marital status, pregnancy, gender expression or identity, sexual orientation or any other legally protected status.

Desired profile

Qualifications

You must possess the minimum qualifications to be initially considered for this position. Relevant experience can be obtained through school work, classes and project work, internships, military training, and/or work experience.

Minimum Requirements:

·  Must have a PhD in Electrical Engineering, Mechanical Engineering, Physics or related field
·  6 months of experience with semiconductor device and layout.
·  6 months of experience of CAD tools and software, in particular DF2, K2view and Hercules.

Preferred Qualifications:

·  Basic knowledge of device physics and parametric analysis.
·  Basic knowledge of photolithography and reticle creation.
·  Familiarity of Tape-out, OPC and Mask Generation Flows for High volume manufacturing.
·  Good understanding of GDS2/SF/OASIS format & layout hierarchy & layer maps.
·  Knowledge of DFII, K2VIEW and other Industry standard CD capture/measurement tools
·  Experience with DRC/LVS, can fix most DRC/LVS issues that come up work with the LVS/DRC maintenance group to build new models as needed.