Design for Test (DFT) Engineer

Job description

Job Description

The main areas of responsibility would be:

- SoC DFT architecture specification including test muxing and DfT RTL coding

- IEEE1149.1 Boundary Scan design

- Scan Insertion, ATPG, scan verification and pattern generation

- Memory BIST insertion, validation and pattern generation

- Functional Pattern generation

- Pattern debug on ATE

- Design Verification for DFT

- ATE correlation activities on bench validation environment

Inside this Business Group

The Platform Engineering Group (PEG) is responsible for the design, development, and production of system-on-a-chip (SoC) products that go into Intel's next generation client and mobile platforms. PEG strives to lead the industry moving forward through product innovation and world class engineering.

Desired profile

Experience with handling full spectrum of DFT activities for a SoC
- Hands-on work experience with at least two of these selected tools:
- Tessentshell/Testkompress for ATPG
- Tessent MBIST
- Cadence NCSIM
- Synopsys DFTMAX and TetraMAX

Competence in two or more of the following areas:
- RTL coding and block-level microarchitecture
- RTL and gate level verification
- DFT insertion and ATPG
- MBIST insertion and validation