Design Automation Engineer
Graduate job Santa Clara (Santa Clara County) Design / Civil engineering / Industrial engineering
Job description
Job Description: Come join Intel's Platform Engineering Group organization as a Design Automation Engineer . In this role you will support the key iHDK/HDK environments. Looking for an experienced Design Automation Engineer to join SDG TFM (Tools Flows & Methods) team to develop/deploy/oversee Data base, Environment, and Central Run methodology.
Activities include:
- Problem analysis and requirements definition, followed by design, implementation, test, deployment, and technical support of the flows.
- Drive tasks related to the HDK and iHDK alignment.
- Provide the Design Automation support to Hard-IP, Soft-IP, Sub-systems, and SoC in SDG.
- Interact closely with HIP and SoC design teams to mature the CAD solutions for production use.
- Support SDG central runs and execution.
- Define and develop methodologies/processes to enable better utilization of CAD tools to improve design efficiency.
- Strong background in pre-silicon validation with successful track record of delivering high quality designs.
The ideal candidate should exhibit the following behavioral traits:
- Problem-solving skills
- Ability to multitask
- Strong written and verbal communication skills
- Ability to work in a dynamic and team oriented environment
Desired profile
You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Experience listed below would be obtained through a combination of your school work/classes/research and/or relevant previous job and/or internship experiences.
Minimum Qualifications:
- BS or a MS degree in Electrical engineering, computer science, computer engineering, or related degree
-Minimum 3 month experience with coding skills in web interface, Java, mysql, linux, perl, and wiki.
-Minimum 3 month experience with semiconductor physics.
-Minimum 3 month experience with digital circuit and layout design.