CPU Validation Engineer
Austin (Travis County) Design / Civil engineering / Industrial engineering
Job description
Job Description
Come join Intel's Atom CPU team in IACG organization as a CPU Validation Engineer. You will be responsible for:
· Developing pre-Silicon functional validation tests to verify system to meet design requirements
· Creating test plans for RTL validation, defining, and running system simulation models
· Finding and implementing corrective measures for failing RTL tests
· Analyzing and using results to modify testing
· Development of CPU verification test bench, test plans, tests, coverage monitors/assertions, and infrastructure
· Debug failing tests in CPUsimulation/emulation/siliconenvironment
· Work with designers and architects to resolve bugs
Inside this Business Group
The Platform Engineering Group (PEG) is responsible for the design, development, and production of system-on-a-chip (SoC) products that go into Intel's next generation client and mobile platforms. PEG strives to lead the industry moving forward through product innovation and world class engineering.
Posting Statement. Intel prohibits discrimination based on race, color, religion, gender, national origin, age, disability, veteran status, marital status, pregnancy, gender expression or identity, sexual orientation or any other legally protected status.
Desired profile
Qualifications
· Bachelors or Master's Degree in Electric Engineering, Computer Science, Computer Engineering
· 0-4 years of experience in validation, preferably on the CPU including experience in the area of test bench development
· Experience in CPU micro-architecture knowledge in areas such as out-of-order execution, processor pipelines, Memory load and store, Cache Coherency, Paging etc.
Preferred Qualifications
· Experience in test bench architecture and hands-on development of components: BFMs, checkers, transactors, monitors and others using verification methodologies like System-Verilog VMM/OVM/UVM or equivalent
· Experience of Pre-Si System Verilog RTL verification flow and environments, including test plans, test writing, and Coverage
· Experience in SoC memory subsystem design or validation
· Knowledge of CPU assembly, Verilog and/or System Verilog, OVM, hardware modeling, and Assertions
· Proficiency in independent debug of System Verilog RTL failures to root-cause functional bugs
· Directed or Constrained-Random test-writing skills