CET Engineer

Job description

Job Description

F68 Technology and Strategy Office (TSO) at Intel Dalian is forming a new engineering team with focus on manufacturing cost reduction through innovation, product enhancement, as well as developing and enabling equipment and process capabilities for future generations of 3D NAND technologies.

This job requisition is look for multiple candidates for the positions of Yield Engineer, FA Engineer, Defect Reduction Engineer, Integration Engineer, Device Engineer, Quality and Relibility Engineer, and Test Engineer , reporting to Integration or Device Engineering Managers in TSO.

Examples of scope of work include silicon process improvement and product enhancement, device capability evaluation and expansion, and wafer cost reduction.

Candidates must have demonstrated a track record of excellence in creative problem solving, device or test capability enabling, or manufacturing process optimization in a relevant engineering organization.

Responsibilities include:

·  Perform feasibility study and provide integrated process solutions to meet desired device specification and process improvement requirements
·  Lead new device experimentation, implementation and high volume manufacturing readiness in the area of expertise
·  Define, explore and qualify new integrated process solutions to meet quality and output needs of new processes for high volume manufacturing ramp.

An expatriate assignment of up to 2 years might be required for qualified internal candidates.

Inside this Business Group

Non-Volatile Solutions Memory Group: The Non-Volatile Memory Solutions Group is a worldwide organization that delivers NAND flash memory products for use in Solid State Drives (SSDs), portable memory storage devices, digital camera memory cards, and other devices. The group is responsible for NVM technology design and development, complete Solid State Drive (SSD) system hardware and firmware development, as well as wafer and SSD manufacturing.

Posting Statement. Intel prohibits discrimination based on race, color, religion, gender, national origin, age, disability, veteran status, marital status, pregnancy, gender expression or identity, sexual orientation or any other legally protected status.

Desired profile

Qualifications

Technical Qualifications

--BS, MS, or PhD in a science or engineering field and minimum 3 years of experience in semiconductor research, development or manufacturing environment are required;

--Demonstrated technical leadership and a track record of problem solving with creativity and out-of-box thinking

--Hands-on experiences in technology development, technology transfer or startup are required

--Strong expertise of process characterization, qualification and troubleshooting is required;

--Direct experience in Silicon Process Technology Development is highly desired.

Other Qualifications

--Motivated self-starter, with strong ability to work independently as well as in a team environment;

--Strong verbal and written communication skills in English;

--Think and operate independently, while simultaneously focusing on many diverse priorities.

--Flexibility and maturity in facing uncertainties and changing priorities/responsibilities

--Commit to aggressive goals and win with a can-do attitude

--Act with velocity and a strong sense of urgency

--Respect cultural diversity and sensitivity

--Agility in learning, improving, and innovating