Exploring pipelining methods for a variable-width high-precision floating point arithmetic unit H/F
Stage Grenoble (Isère)
Job description
Vacancy details
General information
Organisation
The French Alternative Energies and Atomic Energy Commission (CEA) is a key player in research, development and innovation in four main areas :• defence and security,
• nuclear energy (fission and fusion),
• technological research for industry,
• fundamental research in the physical sciences and life sciences.
Drawing on its widely acknowledged expertise, and thanks to its 16000 technicians, engineers, researchers and staff, the CEA actively participates in collaborative projects with a large number of academic and industrial partners.
The CEA is established in ten centers spread throughout France
Reference
2024-34624Description de l'unité
Au sein de CEA Tech, le pôle « recherche technologique » du CEA, l'institut List dédie ses activités aux systèmes numériques intelligents. Nous avons un savoir-faire issu d'une culture de l'innovation et avons pour mission de produire et de transférer les technologies utiles à nos partenaires industriels.
Le Laboratoire Systèmes-sur-puce et Technologies Avancées (LSTA) a pour mission d'étudier, concevoir et implémenter des architectures multi-cœurs et des accélérateurs haute performance. Il exploite pour cela les dernières technologies avancées disponibles : CMOS jusqu'au nœud 7nm, intégration 2.5D/3D, mémoires non-volatiles, ainsi que des puces FPGA. Les domaines applicatifs des architectures développées sont ceux du calcul haute-performance (HPC – High Performance Computing), de l'intelligence artificielle (IA) et du quantique (contrôle numérique de circuits quantiques CMOS).
Position description
Category
Micro and nano technologies
Contract
Internship
Job title
Exploring pipelining methods for a variable-width high-precision floating point arithmetic unit H/F
Subject
Many scientific computing applications are based on the resolution of linear systems by iterative methods. This step consumes the majority of the computation time. Extending the computation precision can reduce the execution time. For this purpose, the LSTA has developed the VRP, a RISC-V processor with a special purpose hardware floating-point unit supporting floating-point values with a mantissa with precision up to 512 bits. To compute at such high precision, operations are implemented internally by iterating on chunks of data, using smaller 128-bit fixed-point operators. This chunk-based approach imposes a minimal impact on operating frequency.
We propose an internship focused on optimizing the internal pipelines of this floating point unit, to further reduce the area footprint and maximize the hardware re-use.
Contract duration (months)
6
Job description
The LSTA laboratory (Advanced Technologies and Systems-on-chip Laboratory) works on the development of innovative chips for various application domains: Artificial Intelligence, High Performance Computing (HPC) and Quantum computing.
Many scientific computing applications are based on the resolution of linear systems by iterative methods. This step consumes the majority of the computation time. Extending the computation precision can reduce the execution time. For this purpose, the LSTA has developed the VRP, a RISC-V processor with a special purpose hardware floating-point unit supporting floating-point values with a mantissa with precision up to 512 bits. To compute at such high precision, operations are implemented internally by iterating on chunks of data, using smaller 128-bit fixed-point operators. This chunk-based approach imposes a minimal impact on operating frequency.
We propose an internship focused on optimizing the internal pipelines of this floating point unit, to further reduce the area footprint and maximize the hardware re-use.
Tasks to achieve during the training period are:
- Master the existing RTL design and the floating point operators
- Modify the existing design by
- Reducing the size of the internal buffers and fixed-point operators
- Modify the control logic of the iterative floating-point operators.
- Maximize the design working frequency by iterating between design, validation, and synthesis.
- Benchmark the modified design against the existing one using benchmark programs.
This internship will allow the candidate to work on different hardware design aspects, from design requirements, RTL coding, logic synthesis, FPGA prototyping and benchmarking of real applications.
This internship takes place at the CEA’s Grenoble research center. The candidate will be part of a team, which is at the state of the art in the domain of extended precision arithmetic for high performance computing.
Methods / Means
VHDL, SystemVerilog, C, C++, Vivado HLS, Questasim (Mentor), DesignCompiler (Synopsys)
Applicant Profile
We are looking for a student in the final year of an engineering degree or a master level student with knowledge in RTL design development (VHDL/Systemverilog), RTL synthesis (Design Compiler), and FPGA emulation (Xilinx Vivado), preferably under Linux.
In line with CEA's commitment to integrating people with disabilities, this job is open to all.
Position location
Site
Grenoble
Job location
France, Auvergne-Rhône-Alpes, Isère (38)
Location
Candidate criteria
Languages
- English (Fluent)
- French (Beginner)
Prepared diploma
Bac+5 - Diplôme École d'ingénieurs
Recommended training
diplôme d'école d'ingénieur ou master 2 informatique/électronique
PhD opportunity
Non
Requester
Position start date
03/03/2025
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