ASIC Verification Enigneer

Job description

Eviden is an Atos Group business with an annual revenue of circa € 5 billion and a global leader in data-driven, trusted and sustainable digital transformation. As a next generation digital business with worldwide leading positions in digital, cloud, data, advanced computing and security, it brings deep expertise for all industries in more than 47 countries. By uniting unique high-end technologies across the full digital continuum with 55,000 world-class talents, Eviden expands the possibilities of data and technology, now and for generations to come.

 

 

 

Total Experience - 3-5 years

 

Job Location - Bangalore

 

Educational Qualification – Only B.E/B.Tech 

 

Main responsibilities:

·  Acquire knowledge microarchitecture an ASIC unit by studying the specification and interacting with the logical design team.
·  Write and perform the test plan in close cooperation with the logical design team.
·  Develop coverage models and verification environments using UVM-SystemVerilog / C++. Write, maintain and publish the verification specification.
·  Monitor, analyze and debug simulation errors.
·  Monitor and analyze simulation coverage results to improve tests accordingly thereby achieving coverage targets on time.
·  Produce a maintainable and reusable code across projects

 

Skills and capacities:

·  Curious, demanding and rigorous.
·  Mastering object oriented programming.
·  Knowledge of UVM verification methodology (or equivalent) and SystemVerilog / SystemC hardware verification languages ​​
·  Knowledge of Constraint-Random / Coverage-Driven verification environments development in SystemVerilog / C ++ (drivers / monitors, constraint random tests, checkers and self-checking models and coverage models written in SystemVerilog-Covergrourp / SVA)
·  Knowledge of simulation tools and coverage database visualization tools
·  Effective in problems solving by rapidly identifying their root cause and developing patches or workarounds under tight timing constraints.

Educational Qualification – Only B.E/B.Tech 

Main responsibilities:

·  Acquire knowledge microarchitecture an ASIC unit by studying the specification and interacting with the logical design team.
·  Write and perform the test plan in close cooperation with the logical design team.
·  Develop coverage models and verification environments using UVM-SystemVerilog / C++. Write, maintain and publish the verification specification.
·  Monitor, analyze and debug simulation errors.
·  Monitor and analyze simulation coverage results to improve tests accordingly thereby achieving coverage targets on time.
·  Produce a maintainable and reusable code across projects
· 

Skills and capacities:

·  Curious, demanding and rigorous.
·  Mastering object oriented programming.
·  Knowledge of UVM verification methodology (or equivalent) and SystemVerilog / SystemC hardware verification languages ​​
·  Knowledge of Constraint-Random / Coverage-Driven verification environments development in SystemVerilog / C ++ (drivers / monitors, constraint random tests, checkers and self-checking models and coverage models written in SystemVerilog-Covergrourp / SVA)
·  Knowledge of simulation tools and coverage database visualization tools
·  Effective in problems solving by rapidly identifying their root cause and developing patches or workarounds under tight timing constraints.

 

 

Let’s grow together.