Verification Engineer (Architecture Verification)

Job description

Job Description

Role Purpose

The Architecture and Technology Group at ARM is responsible for developing technologies and products for ARM’s future architecture roadmap. The Architecture Verification product group at ARM develops Architecture Compliance Kits that are deployed by multiple development teams to prove that implementations are compliant to the ARM architecture rules. This role gives an opportunity to work on the latest Architecture of the ARM Cores & System IPs. ARM Architecture Verification Engineers are required to develop Strong ARM Architectural Knowledge and apply both hardware and software verification skills to develop high quality and reliable IP. They work as part of the architecture verification team to ensure that all areas of the architecture are understood and thoroughly validated. A suitable candidate for this role must possess good engineering and technical skills, fair understanding of CPU architecture and microarchitectures skills and communication skills.

Role & Responsibilities

·  Co-ownership of Architecture Verification Testbench written in SystemVerilog and Verilog
·  Professional and enthusiastic approach to work

Characteristics & Requirements

·  Expertise in different RTL level verification environments, methodology & toolchains (VCS or MTI and Verdi)
·  Strong digital logic design knowledge
·  Expertise on Verilog and System Verilog
·  Basic knowledge of C++ and SystemVerilog DPIs
·  Working knowledge of waveform level debugging
·  Exposure of build and regression flow
·  Self-motivated and willing to take up additional responsibilities to contribute to the team’s success.

Job Requirements

Qualification & Experience

·  Btech/B.S. or MTech/M.S. in Electrical/Electronics Engineering.
·  2+ Years of engineering experience in Verification Tools/Methodology

Job Requirements

Essential Skills and Experience

·  Hands on experience on RTL verification testbenches and flows
·  Hands on experience on writing testbench components in Verilog and SystemVerilog

Desirable Technical skills

·  Experience in SoC/ASIC integration flow and architectures
·  Familiarity in ARM/CPU Architecture verification
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Benefits

Your particular benefits package will depend on position and type of employment and may be subject to change. Your package will be confirmed on offer of employment. ARM's benefits program provides permanent employees with the opportunity to stay innovative and healthy, ensure the wellness of their families, and create a positive working environment.

·  Annual Bonus Plan
·  Restricted Share Units (RSU)
·  Employee Share Purchase Plan (ESPP)
·  Contributory Pension
·  Insurance, Medical, Life & Personal accident
·  Holiday, 25 days annual leave
·  Sabbatical, 20 business days every four-year of service
·  Volunteering, One (1) paid working day each year (TeamARM)
·  Others, subsidized meal, gym, team and social events

About ARM

ARM® is at the heart of the world's most advanced digital products. Our technology enables the creation of new markets and transformation of industries and society. We design scalable, energy efficient-processors and related technologies to deliver the intelligence in applications ranging from sensors to servers, including smartphones, tablets, enterprise infrastructure and the Internet of Things.

Our innovative technology is licensed by ARM Partners who have shipped more than 50 billion Systems on Chip (SoCs) containing our intellectual property since the company began in 1990. Together with our Connected Community, we are breaking down barriers to innovation for developers, designers and engineers, ensuring a fast, reliable route to market for leading electronics companies.

With offices around the world, ARM is a diverse community of dedicated, innovative and highly talented professionals. By enabling an inclusive, meritocratic and open workplace where all our people can grow and succeed, we encourage our people to share their unique contributions to ARM's success in the global marketplace.