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People in our Client Delivery & Operations career track drive delivery and capability excellence through the design, development and/or delivery of a solution, service, capability or offering. They grow into delivery-focused roles, and can progress within their current role, laterally or upward.
Software Engineering professionals work across the Service Delivery Lifecycle to analyze, design, build, test, implement and/or maintain multiple system components or applications for Accenture or our clients.
The Application Development Senior Analyst develops and designs technologies that improve the way our clients and the world works. Supporting the core of Accenture's Technology business, they are eager to learn and use that curiosity to solve Technology problems through developing, designing, and configuring software products or systems that enable client strategies. They use their versatility and experience to design technology solutions that meet client requirements from analysis to implementation.
· Develop and own physical design implementation of multi hierarchy low power designs including physical aware logic synthesis, design for testability, floor plan, place and route, static timing analysis, IR Drop, EM, and physical verification in advanced technology nodes
· Resolve design and flow issues related to physical design, identify potential solutions, and drive execution
· Deliver physical design of an end to end IP or integration of ASIC SoC design
Ideal candidate profile
· Minimum of 3+ years of experience in the RTL2GDSII flow and design tapeouts in 16nm 14nm or below process technologies
· Minimum of 3+ years of experience with low power implementation, power gating, multiple voltage rails and UPF CPF
· Minimum of 3+ years of experience working with EDA tools like DC Genus, ICC2 Innovus, Primetime, Redhawk Voltus or Calibre
· Minimum of 3+ years of experience with Python, TCL or Perl programming
· Bachelor's Degree or equivalent work experience (12 years) or an Associate's Degree with 6 years of work experience.
· Experience in running physical aware logic synthesis and achieving optimal synthesis QoR on low power designs
· Knowledge of static timing analysis and concepts, defining timing constraints and exceptions, corners voltage definition
· Experience in Block level and Full chip floor planning, power grid planning
· Experience with custom or regular clock tree synthesis implementation at block level or top level, and clock power reduction techniques
Applicants for employment in the US must have work authorization that does not now or in the future require sponsorship of a visa for employment authorization in the United States and with Accenture.
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