Intern
05-2016 - 12-2016 Energy / Materials / Mechanics Testing and verification of a Digital Down Converter (DDC) block within AD9625, a
12-bit monolithic sampling analog-to-digital converter in VHDL platform
Design of components for All Digital Phased Locked Loop (ADPLL) in VHDL
platform
Characterisation of an Applied Specific Integrated Circuit (ASIC) in laboratory