Offers “STMicroelectronics”

Expires soon STMicroelectronics

SOC DFT Engineer M/F

  • Greater Noida, INDIA
  • IT development

Job description

General information



Job level

40 - Experienced

Position description

Posting title

SOC DFT Engineer M/F



Contract duration (nb of months)


Job description

About MDG :

Microcontrollers & Digital ICs Group (MDG) contributes to many of ST’s strategic goals for Industrial, Personal Electronics and Communications Equipment. MDG represents about one third of ST’s business.

MDG represents around 3 000 employees (mainly R&D teams in France) located in 40 countries, with a revenue of above 3 billion dollars in 2020. It is addressing 2 major activities: first, General Purpose (GP) Microcontrollers, Memories and Secure Micro (MMS Subgroup) covers all products based on Non-Volatile Memory technologies. It represents 80% of MDG business and second, The RFC Sub-Group focusing on Radio Frequency, Digital & Mixed Signals activities, represents 20% of MDG business.


About MDG/GPM :

The General-Purpose Microcontroller Sub-Group (GPM) is the largest division at ST Microelectronics and the world leader in the microcontroller market supported by our STM32 products.

Leader in the Internet of Things market which is a rapidly expanding sector driven by strong growth, GPM Division asserts its ambition in the Microcontroller market (STM32) by continuing to innovate and to bring tomorrow's solutions.

Passionate & motivated join our team of state of the art engineers.


Role & Responsibility :

As SOC DFT Engineer, you'll be responsible for DFT of STM32 SOCs including: 

- Set up DFT flow, Scan insertion, MBist generation insertion and Boundary scan implementation at fullchip level

- DFT RTL coding and integration. DFT DRC/Linting checks. Create DFT modes timing constraints

- Implement & Debug iJTAG and IEEE 1149/1500 core wrapper-based architecture

- SCAN and Logic-BIST insertion

- ATPG - Pattern Generation, Verification at fullchip level & Pattern Diagnosis & Debug ATE pattern failures.

- High Speed interface DFT management and Analog Test Strategy

- Support other SOC functions (FE Design, Physical Design) End and Test Engineers 


You'll be working in an empowered environment with state of the art methodologies and tools, to contribute to STM32 worldwide success.

A multicultural environment and its diversity are the strength of our dynamic team. A structured development plan will evolve with you along all your career.

We are looking for people with enthusiasm, constantly curious and creative towards continuous innovation, with good communication skills.

Join & Grow with us!


Educational Qualification :

Bachelors/Masters in Electronics/Electrical Engineering


Technical Skills/Knowledge Requirements :

- DFT Fundamentals

- Good RTL (VHDL or Verilog) skills. SOC integration and RTL modification as per DFT requirement

- Knowledge to use industry standard tools like Tetramax, Design Compiler, etc. Experience in follow-up/closure of tool issues with EDA CAD vendors  

- Knowledge in RTL, Gate-level simulations and debug, including silicon-debug

- Knowledge of Boundary Scan Testing and testing of IPs viz ADC, FLASH , PMU in standalone mode.

- Expert in ATPG coverage analysis to achieve high test coverage at SoC level.

- Competence in DFT DRC/Linting/Spyglass checks

- Knowledge in scripting language (TCL, Python, etc.), latest technique (e.g. Lowpower ATPG, Analog Bist, Logic Bist), High-Speed interface testing is a plus


Personality & Soft Skill Requirements :

- Good communication and interpersonal skills.

- Excellent team player & collaborative attitude

- Passionate and motivated to make a difference

- Proactive, Enthusiastic, Creative & Innovative


Position location

Job location

Asia-Pacific, India, Greater Noida

Candidate criteria

Education level required

4 - Bachelor degree

Experience level required

2-5 years


English (2- Business fluent)


Desired start date


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