Offers “STMicroelectronics”

40 days agoSTMicroelectronics

Master 2 / Last Year Engineering School - Technology CAD Engineer M/F

  • Stage
  • Design / Civil engineering / Industrial engineering

Job description

General information


  Location:  Europe, France

Type of contract: Temporary

Job open date: 03/12/2021

Company department:  Technology CAD Engineer


 STMicroelectronics is a leading semiconductor company, a world key player thanks to our 43,200 employees including 8,300 working in R&D.

 ST’s products are found everywhere today. And together with our customers, we are enabling smarter driving, homes, factories, and cities, along with the next generation of mobile and Internet of Things devices. Everywhere microelectronics makes a positive contribution to people lives, ST is there.

 In 2018, we were ranked by the Randstad Employer Brand Research Award among the 5 most attractive companies in France, for our values of excellence, our integrity and the respect of our employees.



The new generation of Si/SiGe HBT transistors is the key element to meet the needs of high-speed communications systems and high data rate required for the integration of heterogeneous intelligent systems as well as for intelligent mobility systems that will be used in future fully automated transport systems. The main objective of this internship is to contribute to the development of HBT transistors offering high maximum oscillation frequency (Fmax> 400GHz) remaining compatible with very high density platforms like 55 nm and 28nm FD-SOI CMOS.
A preliminary study has already been carried out in collaboration with the IMS laboratory in Bordeaux on a promising new transistor design (patent pending). The simulations carried out so far do not take into account technological constraints in the sense that the structure has been idealized. For example, the doping profiles are simplified as well as the dielectric stack, the access to the transistor (BEOL) or the thermal budget. A more realistic process must therefore be taken into account when building this innovative HBT device considering the technological constraints imposed by the process line at STMicroelectronics. Once the technology process simulation is completed, the electrical figures of merit will be re-simulated to evaluate the promises of this approach. In successive optimization loops the device performances will be boosted. The student will be hosted at the IMS laboratory in Bordeaux during the internship period in order to benefit from the Bordeaux research group's experience in transistor modeling.
This internship would be a preliminary step before the start of a CIFRE PhD thesis which aims at the development and clean room fabrication of the most advanced prototypes of HBT Si/SiGe transistors.



·    The candidate must have strong knowledge in semiconductor technological processes and transistor physics. Competencies in simulations tools will be appreciated. Good methodology and communication skills are mandatory.
·   5 - Master degree
·   Less than 2 years



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