Offers “STMicroelectronics”

39 days agoSTMicroelectronics

Front-end Digital Designer M/F

  • Catania (Catania)
  • Teaching

Job description

General information

Reference

2021-11706  

Job level

080 - Technical Non-Exempt

Position description

Posting title

Front-end Digital Designer M/F

Regular/Temporary

Regular

Job description

Introduction.

The position is an exciting opportunity to be part of a flexible and dynamic team in the growing markets of mixed signal chips with signal processing IPs, ARM processor and AMBA bus interface like Wireless Chargers, Bluetooth, PMIC etc. used in Mobile, Tablets, Microcontrollers etc. The role works within the digital design team with the aim to create an efficient Digital Design.

 

 

Job scope.

• Work at IP level design, but occasionally also at SOC design.

• Creation of RTL code

• Some opportunities to integrate the IP in the SOC

• UPF flow, Low power Flow, Power aware simulations

• CDC/RDC/LINT checks using various tools

• Verification of concept using Matlab/Simulink and toolboxes

• Opportunities to run HLS and HLV platforms like Catapult.

• Synthesis, Scan insertion, ATPG.

• STA.

• Schedule preparation at IP level together with the Design leader and execution adhere to plan.

• Reporting to the management.

• Accountability.

Profile

• Masters in Electronics' Engineering (a relevant experience with minimum 2 years in a

semiconductor or high technology R&D environment would be appreciated)

• Some Knowledge of ARM based Architectures, AMBA bus, Peripherals, Boot would be appreciated

• Some Knowledge of RISC-V architectures would be appreciated.

• Some Experience in Hardware Design Language (such as VHDL or Verilog).

• Some Experience in CDC, RDC, LINT would be appreciated

• Some Experience in Synthesis, Scan Insertion, ATPG.

◦ Some exposure to Physical Design, including Power analysis, Clock tree Synthesis, Physical Checks would be appreciated

◦ Some exposure to Power Aware, Low power and UPF methodology would be appreciated

◦ Some knowledge of tools porting from Verilog RTL into C++ would be appreciated.

◦ Some exposure to Scripting languages (PERL, TCL, PYTHON) would be appreciated

• Knowledge in Static Timing Analysis

• Good communication and written skills in English.

• Able to work in a multi-cultural team.

• Strong analytical and problem-solving skill.

• Able to keep up with fast moving new design methodology.

 

The Employment search is addressed to candidates of both genders, under Law 10.04.1991 n. 125, as amended by Legislative Decree n. 198/2006 which guarantees gender equality at work

Position localisation

Job location

Europe, Italy, Catania

Candidate criteria

Education level required

5 - Master degree

Experience level required

2-5 years

Requester

Desired start date

01/06/2021

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