Digital Design FE M/F

Job description

General information

Reference

2020-7507  

Job level

080 - Technical Non-Exempt

Position description

Posting title

Digital Design FE M/F

Regular/Temporary

Regular

Job description

We are looking for a digital design for PCM memory IP, interested in RTL simulation, verification and silicon validation of test chips. The candidate will join the Smart Power Technology in the PCM Design Team in Agrate with interaction with teams located in different countries and different organizations.

PCM memory are specific Non Volatile Memories (NVM) IPs designed in advance BCD technology nodes like BCD10 and C090D. Products and Applications complexity is expanding and so the need of non volatile memory is rapidly increasing in all areas of the four market segments addressed by ST: Automotive, Industrial, Personal Electronics, Communications Equipment Computers&Peripherals.

Embedded PCM IPs are an added value in SOCs and the design team is continuously focus on improvement for a better performance.

 

Profile

The position requires skills in all areas of design, characterization, test and technology understanding. Technical skills required are:

Master Degree in Semiconductor, Electronics Engineering area
Knowledge in RTL language (Verilog, System Verilog and VHDL)
Knowledge of DFT technique and tools (Scan, ATPG, JTAG, LBIST, DFT architecture)
Knowledge of Memory BIST architecture and tool
Knowledge in scripting language for automation (TCL, perl, ..)
Knowledge in analog design is also an asset for this position.
Characterization and Lab activity
fluent written/spoken English
Strong team spirit, teamwork capability

Position localisation

Job location

Europe, Italy, Agrate

Candidate criteria

Education level required

5 - Master degree

Experience level required

Less than 2 years

Requester

Desired start date

01/07/2020