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Stage - Design of floorplanning techniques for Partially-Reconfigurable FPGA targeting 5G use cases F/H

  • Stage
  • Cesson-Sévigné (Ille-et-Vilaine)

Job description

about the role

With the emergence of 5G, new opportunities for hardware acceleration arise, both at the level of radio access network infrastructure (physical layer functions such as 5G LDPC and FFT) and at the service layer (computer vision, deep learning networks). In order to reduce costs and energy consumption, we aim at sharing hardware resources across different accelerators (functions implemented on FPGAs) using dynamic and partial reconfiguration which allows reconfiguring selected areas of the FPGA without perturbing currently used accelerators.

 

At Orange we are investigating Xilinx Vitis and Dynamic Function Exchange (DFX) technologies to implement accelerators on disjoint regions of the FPGA to enable both time and space sharing of hardware resources.

When using DFX technology, FPGA sub-regions are usually defined for the target accelerators taking into account the quantity of resources required by every accelerator implemented for that region. Dynamically, only such pre-defined sub-regions can be reconfigured with one of the accelerators implemented for it. We would like to consider the scenario where sub-regions may be merged and/or resized dynamically to be able to configure accelerators implemented for such different region sizes. This requires efficient allocation of FPGA sub-regions and decision on which sub-regions to merge/resize. A key problem is to define each of the reconfigurable regions in terms of their shape and position on the FPGA.

 

This internship is structured in the following phases:

- Firstly, understand constraints related to FPGA region allocation and specifically for partially reconfigurable FPGAs.

- Secondly, formulate the partial regions allocation problem employing a suitable methodology. The model should take into account runtime decisions to merge/resize sub-regions that will be configured with an accelerator implemented to use it. This phase will include literature surveys.

- The final step will propose solutions for the allocation problem. Such a solution may also be tailored for a specific set of accelerators. This step will consist of implementing solutions that may be experimentally validated for a concrete set of accelerators.

about you

Bac + 5 or equivalent in Computer Science, Electronics or Applied Math looking for a 6-month internship in 2023.

Skills and personal qualities:

- Background in reconfigurable hardware such as FPGA and/or operations research.
- Good programming skills
- Curious and motivated
- English level: able to understand scientific papers

department

Le stage est proposé au sein de la division Orange Innovation, dans la direction Networks, qui oriente les choix d'Orange et accompagne ses différentes filiales internationales, notamment sur la mise en place et l'évolution des solutions d'infrastructures d'hébergement pour la virtualisation des fonctions réseaux.

contract

Internship

Level : Master 2

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·  {} : 4 rue du clos Courtel 35510 CESSON SEVIGNE - France  

·  -

Orange

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about the role

With the emergence of 5G, new opportunities for hardware acceleration arise, both at the level of radio access network infrastructure (physical layer functions such as 5G LDPC and FFT) and at the service layer (computer vision, deep learning networks). In order to reduce costs and energy consumption, we aim at sharing hardware resources across different accelerators (functions implemented on FPGAs) using dynamic and partial reconfiguration which allows reconfiguring selected areas of the FPGA without perturbing currently used accelerators.

 

At Orange we are investigating Xilinx Vitis and Dynamic Function Exchange (DFX) technologies to implement accelerators on disjoint regions of the FPGA to enable both time and space sharing of hardware resources.

When using DFX technology, FPGA sub-regions are usually defined for the target accelerators taking into account the quantity of resources required by every accelerator implemented for that region. Dynamically, only such pre-defined sub-regions can be reconfigured with one of the accelerators implemented for it. We would like to consider the scenario where sub-regions may be merged and/or resized dynamically to be able to configure accelerators implemented for such different region sizes. This requires efficient allocation of FPGA sub-regions and decision on which sub-regions to merge/resize. A key problem is to define each of the reconfigurable regions in terms of their shape and position on the FPGA.

 

This internship is structured in the following phases:

- Firstly, understand constraints related to FPGA region allocation and specifically for partially reconfigurable FPGAs.

- Secondly, formulate the partial regions allocation problem employing a suitable methodology. The model should take into account runtime decisions to merge/resize sub-regions that will be configured with an accelerator implemented to use it. This phase will include literature surveys.

- The final step will propose solutions for the allocation problem. Such a solution may also be tailored for a specific set of accelerators. This step will consist of implementing solutions that may be experimentally validated for a concrete set of accelerators.

about you

Bac + 5 or equivalent in Computer Science, Electronics or Applied Math looking for a 6-month internship in 2023.

Skills and personal qualities:


- Background in reconfigurable hardware such as FPGA and/or operations research.
- Good programming skills
- Curious and motivated
- English level: able to understand scientific papers

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