SoC Design Engineer - Pre-Si Validation

Job description

Job Description

Come join Intel's Silicon Engineering Group organization in Pre-Silicon Validation. In this role you will be working as part of a pre-silicon validation team for future Intel SoCs or IPs.

Your responsibilities will include but not be limited to:

• Validation of an IP or feature, either directly or at the system level.
• Creating plans and tests for validating portions of a complex microarchitecture using written specs, RTL code and other tests as a guide.
• Learning the architecture and microarchitecture by debugging failures to the root cause.
• Developing and utilizing various debug and validation tools and/or methodologies to implement validation plans with the goal being to ensure a solid design.
• Participating in the debug of failures on silicon and developing new testing strategies to detect these failures on RTL models.
• Engaging with IP providers and customers to define, develop and deliver necessary infrastructure and address issues found during execution.
• Developing tools and methods to streamline IP development and SOC integration to deliver highest quality in shortest time possible.
• Developing debugging tools and software.

Inside this Business Group

The Silicon Engineering Group is a worldwide organization focused on the development and integration of SOCs, Cores, and critical IPs that power Intel's leadership products. This business group leverages an incomparable mix of experts with different backgrounds, cultures, perspectives, and experiences to unleash the most innovative, amazing, and exciting computing experiences.

Desired profile

Qualifications

Minimum Qualifications

• BS degree + 5 years' experience or MS degree + 3 years' experience in Computer Science, Computer Engineering or Electrical Engineering.
• Minimum 3 years' experience with reading and interpreting technical specs and Register Transfer Level (RTL) code.
• Minimum 3 years' experience working on IP or SoC development, verification, or integration using Verilog/SystemVerilog/ Open Verification Methodology (OVM)/Universal Verification Methodology (UVM).

Additional Profile Characteristics Preferred

• Minimum 3 years' experience with writing validation plans and software to implement those validation plans.
• Minimum 1 year experience with UNIX* or Linux*.
• Minimum 1 year experience with computer architecture.
• Minimum 1 year experience with IA-32 assembly and/or Verilog* programming experience.
• Minimum 3 years' experience with validation or testing experience, especially in a silicon design team.
• Experience in the fields of emulation model builds, memory controllers, or Design For Test