Layout and Design Accelerator (DA) – Silicon Photonics Engineer

Job description

Job Description

The Design Automation and Methodology Engineer will be responsible for enabling flows and methodologies for Optical PDK Designs for Intel's Silicon Photonics Division while being a part of a centralized team under NVM Solutions Group. The qualified Design Automation DA candidates will be responsible to develop, validate/QA and support the custom layout collateral portion of the Optical Process Design Kit PDK. Primary responsibilities will focus on writing the caliber DRC rule file, and running a robust set of QA regression tests that thoroughly test out the quality of the custom layout collateral within the Optical PDK. The candidate will be responsible for developing and managing the design rule document, PDK Pcell development, Electronic Design Automation EDA tools/flows and platforms to ensure high-quality delivery of kit content to customers.

Inside this Business Group

Non-Volatile Solutions Memory Group: The Non-Volatile Memory Solutions Group is a worldwide organization that delivers NAND flash memory products for use in Solid State Drives (SSDs), portable memory storage devices, digital camera memory cards, and other devices. The group is responsible for NVM technology design and development, complete Solid State Drive (SSD) system hardware and firmware development, as well as wafer and SSD manufacturing.

Posting Statement. Intel prohibits discrimination based on race, color, religion, gender, national origin, age, disability, veteran status, marital status, pregnancy, gender expression or identity, sexual orientation or any other legally protected status.

Desired profile

Qualifications

Education:
You must possess a minimum of a Master's Degree of Science degree in Electrical Engineering or Computer Engineering.

Minimum Qualifications:
- 4+ years of experience in IC Design or Computer Aided Design CAD
- 3 + years of experience in setup/use/support of data management tools integrated with virtuoso platform
- 3+ years of experience in scripting skills, especially TCL and PERL Python a plus
- 3+ years of experience in either/and/or below:
Circuit simulation flows development, support and debug.
Parasitic extraction flows, LVS, DRC, flows setup and debug

Additional Requirements:
- Basic understanding of CMOS VLSI, device models, device formation, semiconductor layers
- Strong problem solving skills, ability to multi-task and prioritize tasks
- Proficient in Virtuoso platform - schematic editor, layout editor, ADE environment, tech file, streamIn, verilogIn
- Experience in supporting ADE-L/XL, Spectre simulator, ocean scripting experience is advantageous
- Experience with tsmc, towerjazz, globalFoundary and other external foundries tape-in/tapeout is advantageous
- Demonstrate experience with the Cadence Virtuoso* environment, including Schematic Composer and Layout Editor.
- Ability to work in a dynamic environment and highly self-motivated.
- Self-motivated technical leader.