DFT Validation Engineer

Job description

Job Description

The Santa Clara Design Center's Chassis Design For Test DFT team within SDG is seeking applicants with DFT or Validation experience to make an immediate impact.

The DFT team is responsible for DFT design and validation servicing m server products across Intel. By Joining the team you'll get an opportunity to contribute to the infrastructure that enable manufacturing test teams to reduce manufacturing defects to customers, significantly contributing to Intel's quality and reputation.

This particular job is for Tap network validation owner and will include, but won't be limited, to the following responsibilities:

- Validate proper integration and functionality of DFT features within the reference chassis model by developing tests in an OVM environment.

- Experience with Design-For-Test DFT principles such as SCAN for logic testing, BIST and repair for memory test, JTAG Boundary SCAN, an advantage.

- Develop OVM sequences and scripts while keeping efficiency and re-usability in mind.

- Interact with and support other validation engineers who are making use of DFT flows and IP's within subsystems or SOC's.

- Be able to pick up other tasks within the team, be it design or validation ones.

Inside this Business Group

The Platform Engineering Group (PEG) is responsible for the design, development, and production of system-on-a-chip (SoC) products that go into Intel's next generation client and mobile platforms. PEG strives to lead the industry moving forward through product innovation and world class engineering.

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Desired profile

- BS or MS in Electrical Engineering or Computer Engineering and 3+ years of experience in design or validation- Good team work ability, be able to get the support you need and provide support for others- Good communications skills, report back status and raise flags where needed- Excellent problem solving skills, self-learner and fast performer, innovative and able to drive others