DFT DA engineer

Job description

The position is in Intel's Platform Engineering Group (PEG) centralized engineering group and part of the Client and Devices Design Group. As part of the central DFT platform development team, the candidate will support the Central DFT methodology team by enabling design infrastructure, developing/deploying tools, and collaborating to develop solutions to help accelerate DFT methodology deployment. You will work closely with design engineers to maximize the efficiency of the design process.
Responsibilities would include:
- Improve design environment and design efficiency for DFT deployment.
- Define, investigate and provide solution/approaches of technical EDA challenges which involve problem analysis and requirements definition, followed by design, implementation, testing, deployment, and technical support to enable better utilization of DFT tools.
- Collaborate with product design teams on methodology development, provide design automation deployment support, and interact closely with customers and DFT leadership to help mature the DFT methodologies for production use.
- Provide training, documentation and other collaboration sessions to the design teams as necessary to learn new flows and improve design efficiency.

Desired profile

Minimum Requirements:
-Must have a MSEE degree in Computer Science, Computer Engineering, or Electrical Engineering with a minimum of 2 years or BSEE degree with a minimum of 4 years of industry experience in CAD and chip design to include the following skillsets:
-Minimum of 2 years of experience in CAD Software development, flows and architecture as well as CAD/DA tools/flows support

-DFT EDA tools

-CAD development, Perl, TCL, DA tools, C++, Object oriented
-Strong proficiency in shell scripting and scripting programming languages (Perl/Python/Ruby/Tcl) in Unix-based environments
-Experience developing design environments for Analog, Digital and Backend design groups including design verification and ERC checks or circuit simulation tools.
-Experience with EDA vendors tools and methodologies related with Analog, Digital and Backend design groups

*LI-USA-BH1