ARM SoC Architect - Intel - Austin

Job description

Job Description

The SoC architecture team of the Intel Programmable Solutions Group (PSG) defines the hardened processor subsystems (HPS) within FPGA SoC devices. The HPS consists of multicore processors, multi-level memory hierarchies, standardized peripherals as well as a high-performance interface that allows the FPGA fabric and HPS perform cooperative processing. In addition to the HPS, these FPGA SoC devices have a Secure Device Manager SDM that performs FPGA configuration, processor boot, device root-of-trust and security, device power management, as well as provides a variety of device level services. As an SoC Architect, your responsibilities will include, but not limited to:

· Prototyping, modeling and benchmarking of the HPS and SDM for next generation platforms.
· Authoring related architectural and functionalspecifications.
· SupportingRTL, DV, and applications teams throughout development and product life-cycle.

Inside this Business Group

The Programmable Solutions Group (PSG) was formed from the acquisition of Altera. As part of Intel, PSG will create market-leading programmable logic devices that deliver a wider range of capabilities than customers experience today. Combining Altera's industry-leading FPGA technology and customer support with Intel's world-class semiconductor manufacturing capabilities will enable customers to create the next generation of electronic systems with unmatched performance and power efficiency. PSG takes pride in creating an energetic and dynamic work environment that is driven by ingenuity and innovation. We believe the growth and success of our group is directly linked to the growth and satisfaction of our employees. That is why PSG is committed to a work environment that is flexible and collaborative, and allows our employees to reach their full potential.

Other Locations
US, California, San Jose;

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Desired profile

Qualifications

· BSEE, BSCE, BSCS, or related degree
· 6+ years industry silicon architecture or design experience
· 2+ years of experience authoring silicon specifications
· 3+ years of experience in several or all of the following:
· network-on-chip and related protocols AXI, OCP, etc.
· architectures for reset, clocking, and power management
· ARM processor configuration
· standard interfaces such as USB and Ethernet
· functional safety architecture (ISO 26262, ASIL, SIL)
· experience with reading simulating, and debugging with VHDL or Verilog
· experience with hardware security architecture

Preferred (Additional) Qualifications

· MSEE, MSCE, MSCS, or related or higher degree a plus
· 10+ years industry silicon architecture or design experience