Offers “CEA”

Expires soon CEA

Design and optimization of cryogenic SRAM for quantum computing H/F

  • Stage
  • Grenoble (Isère)
  • IT development

Job description

Détail de l'offre

Informations générales

Entité de rattachement

Le Commissariat à l'énergie atomique et aux énergies alternatives (CEA) est un organisme public de recherche.

Acteur majeur de la recherche, du développement et de l'innovation, le CEA intervient dans le cadre de ses quatre missions :
. la défense et la sécurité
. l'énergie nucléaire (fission et fusion)
. la recherche technologique pour l'industrie
. la recherche fondamentale (sciences de la matière et sciences de la vie).

Avec ses 16000 salariés -techniciens, ingénieurs, chercheurs, et personnel en soutien à la recherche- le CEA participe à de nombreux projets de collaboration aux côtés de ses partenaires académiques et industriels.

Référence

2021-19436

Description du poste

Domaine

Composants et équipements électroniques

Contrat

Stage

Intitulé de l'offre

Design and optimization of cryogenic SRAM for quantum computing H/F

Sujet de stage

Design and optimization of cryogenic SRAM for quantum computing

Durée du contrat (en mois)

6

Description de l'offre

For several years, CEA has been working on the development of a quantum computer using FD-SOI technology for the design of computational CMOS circuits. Indeed, this process technology has intrinsic physical properties suitable for operations at cryogenic temperature (mK) required for quantum computation. These computational circuits require relatively fast and energy efficient working memories. In this context, SRAM memories seem to be the most suited to these needs. However, the mainstream bitcell architectures based on 6 transistors need to be further improved, in particular with regard to consumption aspects during write operations. One solution would be to use bitcell architectures based on 4 transistors (driver- or load-less) which allow lower write consumption, but which are less stable in data retention mode at room temperature. Nevertheless, the data stability greatly improves with the drop in temperature, and therefore should be compatible with the cryogenic temperature required for quantum computing.

The different phases of the internship will be as follows:

  1. Design and simulate (at Spice level) 6- and 4-transistor SRAM bitcell architectures in FD-SOI technology at room and cryogenic temperature
  2. Optimize the bitcell sizing and array partionning
  3. Layout and parasitic extraction for post-layout Spice simulations

CEA references:

[1] R. Boumchedda et al., “High Density 4T SRAM Bitcell in 14nm 3D CoolCube Technology Exploiting Assist Techniques”, IEEE TVLSI, Vol. 25, No. 8, Aug. 2017, pp. 2296-2306.

[2] R. Boumchedda et al., “Energy-Efficient 4T SRAM Bitcell with 2T Read-Port for Ultra-Low-Voltage Operations in 28nm 3D Monolithic CoolCubeTM Technology”, NANOARCH, 2018.

[3] F. Andrieu et al., “Design Technology Co-Optimization of 3D-monolithic standard cells and SRAM exploiting dynamic back-bias for ultra-low-voltage operation”, IEDM, 2017.

[4] M. Brocard et al., “High Density SRAM Bitcell Architecture in 3D Sequential CoolCubeTM 14nm Technology”, S3S, 2016.

Moyens / Méthodes / Logiciels

Analog & full-custom design, Spice simulations, Cadence Virtuoso

Desired profile

Profil du candidat

This offer is dedicated to students looking for a technical and ambitious internship. If you are looking for an experience in ASIC design with industrial-grade tools and processes, this internship is perfect for you! The student will be required a master 2 or equivalent level preferably with a specialisation in analog/mixed-signal circuit design. You will work in a multi-disciplinary environment where strong communication skills are an asset. Experience or affinity with memory circuit will be much appreciated.

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