This is a non-SDE role. We are a team of ASIC/FPGA Chip designers and design hardware – not software.
This is a highly specialized skill. We are looking for grad students who have taken 2 graduate level DV (Design Verification) classes.
We are looking for student interns in Summer 2021. This is a unique opportunity to be part of a Pilot program.
ASIC – Full custom chip which is sent to a fab to get manufactured (most schools can’t do this)
FPGA – The student’s hardware design is loaded into a programmable chip called an FPGA.
Amazon AQUA, Advanced Query Acceleration, is a new service offering to the Amazon RedShift data warehouse solution. AQUA is designed from the ground up to enhance performance of analytic query workloads. AQUA achieves high performance by using a highly distributed platform built of the latest generation hardware, specialized Amazon hardware accelerators, and advanced caching techniques. AQUA’s obsession with performance allows customers to experience significantly higher throughput accelerating their ability to answer business questions with more data.
To explore more about Amazon AQUA, visit:
Help us achieve high quality design verification of accelerator IP blocks. In this role you would be required to read the architectural specification and transform that learning into high quality functional coverage and assertion blocks. You would also be involved in running regressions, analyzing coverage holes and writing testcases to achieve full coverage closure. You would also be given the opportunity to help improve our DV methodology through scripting and automation.
· Previous internship experience is a plus. Experience with scripting languages like Python, bash is a plus.
Applications are reviewed on a rolling basis. For an update on your status, or to confirm your application was submitted successfully, please login to your candidate portal. NOTE: Amazon works with a high volume of applicants so we appreciate your patience as we review applications. Amazon is committed to a diverse and inclusive workplace. Amazon is an equal opportunity employer and does not discriminate on the basis of race, national origin, gender, gender identity, sexual orientation, protected veteran status, disability, age, or other legally protected status. For individuals with disabilities who would like to request an accommodation, please visit: https://www.amazon.jobs/en/disability/us.
Pursuant to the San Francisco Fair Chance Ordinance, we will consider for employment qualified applicants with arrest and conviction records. Pursuant to the Los Angeles Fair Chance Ordinance, we will consider for employment qualified applicants with arrest and conviction records.
· Working on Master’s degree or equivalent in Computer Science or Engineering with an anticipated graduation date of October 2021 or later.
· Must have taken graduate level courses in System Verilog and UVM (Universal Verification Methodology).